Trusted Hardware for Partitioned Multicore

This paper aims to give a comprehensive design of the trusted hardware layer for a partitioned multicore processor. We start our design with the Trusted Platform Module (TPM) and propose changes to the TPM architecture that are necessary for a partitioned multicore processor. We propose several security measures to make the system secure against plausible known attacks. We analyze the system implementation trade-offs and provide some simulation results to illustrate them. We also propose a protocol for bulk decryption which combines the security of the TPM with the efficiency of a general purpose CPU. We suggest a number of changes to the hardware and the cryptographic primitives to improve the security and efficiency of the system.